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High performance microcontroller ip cores with native multithreading support

Microcontrollers of Birusinka can execute up to 2 commands per clock, in general require 0 clock cycles to switch to an interrupt routine and support multithreading by hardware. 2-level early branch detection mechanism allows fast executing of jump instructions, so these instructions (may be the most common in most algorithms) often require 0 clock cycles for execution.

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Netlist of a base version of 32-bit microcontroller (+ some periphery) is available.

IDE includes assembler, linker and in-system debugger. There are no limitations of the compiled code size which is limited only by the microcontroller memory.

IDE is available for free download.

 Main features of Birusinka microcontrollers:

  • 8, 16 and 32-bit operations
  • Multithreading support
  • Up to 2 commands per clock
  • Early jump detection, so jump instructions often require 0 clock cycles, even if jump is executed
  • Very fast switch from thread to IRQ routine, which in general requires 0 clock cycles
  • Separate program, data and IO space

What does mean "0 clock cycles" for execution?

In case of jump command it means that microcontroller executes command just before jump and then executes a command where jump targets. So jump command does not require any clock cycle for execution. There can be exceptions when microcontroller will require some additional clock cycles, but in most cases program can be optimized in a way that no additional clock cycles are required.

In case of interrupt request the first command of interrupt routine will be executed immediately after the command of interrupted process. Executed, and not fetched and then decoded and then executed. Feel the difference! There is no need to save registers either.

 What is available

Osinka32-bit microcontroller IP core.
High performance MCU with a native multithread support. Able to execute up to 2 commands per clock, has a 2-level early jump detection mechanism. Operates with 8, 16 and 32-bit integer and 32-bit floating-point data.

Oriole16-bit microcontroller IP core.
High performance MCU, close to Osinka but 16-bit. Able to execute up to 2 commands per clock, has 2-level early jump detection mechanism, supports multithreading. Operates with 8 and 16 bit data.

mce64-bit microcontroller IP core.
64-bit MCU with a native multithread support. Able to execute up to 2 commands per clock, has a 2-level early jump detection mechanism. Operates with 8, 16, 32 and 64-bit integer and 64-bit floating-point data.

Different periphery units: Timers, UART, etc.
Different periphery IP cores are supplied with design examples. Some of them are available as verilog source code. See page Digital for details.

 
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